1. Field of the Invention
The invention relates to the field of MOS floating gate devices.
2. Prior Art
In recent years, numerous metal-oxide-semiconductor (MOS) cells have been developed which employ floating gates for the storage of information. Typically, electrical charge is transferred into an electrically isolated (floating) gate to represent one binary state while an uncharged gate represents the other binary state.
Perhaps the first of these floating gate devices is disclosed in U.S. Pat. No. 3,500,142. In this device tunneling is employed to transfer charge from the substrate into a floating gate through a relatively thin oxide (50 A). Because of the difficulty in fabricating the thin oxide, this device has not been commercially successful. Moreover, because of the thin oxide only relatively short storage times were obtained.
Avalanche injection has also been used to transfer charge from the substrate into a floating gate. This phenomenon allows the use of relatively thick oxides (500 to 1,000 A) and results in long retention times (years). An MOS floating gate device employing avalanche injection for programming is described in U.S. Pat. No. 3,660,819. Channel injection again through a relatively thick oxide, is also used to charge floating gates. For an example of this type of device, see U.S. Pat. No. 3,966,657.
Numerous erasable MOS floating gate devices have been described in the prior art, however, currently the most commonly employed erasing technique for floating gate devices is the exposure of the devices to radiation such as ultraviolet radiation. A device is described in U.S. Pat. No. 3,797,000 which employs avalanche injection for the removal of charge from a floating gate.
In copending application Ser. No. 778,574, filed Mar. 17, 1977 (assigned to the assignee of this application) a floating gate device is described which employs channel injection for charging a floating gate and tunneling for discharging or erasing this gate. Tunneling through a relatively thick oxide from the floating gate is possible with this device since an enhanced electric field is produced by the rough surface on the floating gate.
In the present invention an MOS cell is described which employs tunneling both for charging a floating gate and for the removal of charge from this gate. Enhanced electric fields which result from rough textured gates allow the charging and discharging of the floating gate through relatively thick oxides. In the presently preferred embodiment, the invented device is fabricated from three separate layers of polycrystalline silicon (polysilicon). One application for such a device other than for use in an electrically programmable and electrically erasable read-only memory is for providing discretionary connections. For example, the described device may be used for coupling a redundant row or column in a memory to replace a failed row or column. The invented device is particularly suitable for use with a charge-couple device (CCD) which employs three levels of polysilicon such as the one described in copending application Ser. No. 764,005, filed Jan. 31, 1977 (assigned to the assignee of this application).